A static random-access memory is a volatile semiconductor memory that does not need to be refreshed but that typically loses data when power is removed from the SRAM. FIG. 1 shows an example of a prior art SRAM bit cell that includes a storage cell comprised of metal oxide semiconductor field effect transistors (“MOSFETs”) M1, M2, M3, and M4 that are arranged as two cross-coupled inverters. A MOSFET pass gate transistor M5 couples the storage cell to a bit line BL. A MOSFET pass gate transistor M6 couples the storage cell to an inverse bit line BLB (“bit line bar”). Pass gate transistors M5 and M6 are also referred to as access transistors or pass gates. The word line WL is coupled to the gates of pass gate transistors M5 and M6. The supply voltage VCC is coupled to the storage cell and typically remains constant during standby, read, and write operations.
In the standby mode, the pass gate transistors M5 and M6 disconnect the storage cell from the bit lines BL and BLB.
In the read mode, the bit lines BL and BLB are both precharged to a logical 1. A voltage is applied to the word line WL, enabling both pass gate transistors M5 and M6. The values stored at Q and QB are then transferred to the respective bit lines BL and BLB. If Q is a logical 1, then BLB is discharged through transistors M3 and M6. The bit lines BL and BLB then have a voltage difference between them, which is sensed by a sense amplifier connected to bit lines BL and BLB. Thus, a read operation senses a logical 1 stored in the storage cell. If a logical 0 was stored in the storage cell, then bit line BL would be discharged and a logical 0 would be sensed.
For a write operation writing a logical 0 to the storage cell, the bit line BL would be set to a logical 0 and BLB set to a logical 1. The word line WL is then enabled, causing the values stored on BL and BLB to be latched and stored by the storage cell. The transistors M1, M2, M3, and M4 are relatively weak, allowing them to be overridden by the bit lines. For writing a logical 1, bit line BL would be set to logical 1 and bit line BLB would be set to a logical 0.
Prior art SRAM bit cell design involves finding an operating window where both read and write operations can be performed. An SRAM bit cell needs read stability and the cell needs to be writeable. Those can be competing goals. To make the SRAM bit cell both read stable and writeable, the higher of a read stable and writeable voltage has been used. Prior art pass gates typically have low resistance in order to improve write operations. But the size of the pass gates and the storage cell transistors has to be such that a read operation minimizes the disturbance of charge stored in the cross-coupled inverters of the storage cell. For relatively large prior art SRAM bit cells, the transistors can be chosen in a way that allows reading and writing even with variations in transistor size associated with semiconductor fabrication.
As transistors have become smaller, the operating windows have become so small that meeting the competing goals associated with reading and writing to an SRAM bit cell has typically been increasingly difficult. SRAM bit cells have been made smaller than 0.1 square micrometers (“μm2”) using 22 nanometer (“nm”) technology.
A prior art technique of word line underdrive has been used to reduce the voltage on the word line WL to less than VCC. Word line underdrive typically can be beneficial for read operations by reducing the disturbance on the storage cell transistors. A disadvantage of prior art word line underdrive is that the technique typically involves reducing the word line voltage for both read and write operations, typically resulting in degraded write operations. Prior art word line underdrive relies on there being a sufficient write margin so that writability degradation is not significant. In smaller scales, this assumption may not be true.